PLLs including a local VCO are commonly used for maintaining the output of the VCO in frequency and phase with a reference signal.
Typically, the VCO frequency is compared to a fixed reference frequency in order to generate a signal that modifies the VCO frequency up or down until the comparator inputs are not only of the same frequency but also in phase. Such phase-frequency detectors are known, see for example Motorola MC4044, MECL Databook DL122 Rev. 3 Q2/88, and are disclosed for example in U.S. Pat. No. 5,631,582 granted May 20, 1997 to Akio Fujikawa.
As taught by Fujikawa, a circuit as illustrated in FIG. 1 herein and in FIG. 1 of U.S. Pat. No. 5,631,582 is used as a phase-frequency comparator. Reference numerals 20 and 21 represent D-type flip-flops, reference numeral 22 represents an inverter, reference numeral 23 represents an AND gate, reference numeral 26 represents a P-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and reference numeral 27 represents an N-type MOSFET. Reference numerals 28a, b and c represent power terminals connected to a power source V.sub.DD.
The flip-flop 20 has its D input terminal pulled up by the supply voltage V.sub.DD through a terminal 28a. To its clock terminal C a digital reference signal F.sub.REF is input. The output from the Q terminal of the flip-flop 20 is input to the inverter 22 through a node A and coupled to one input terminal of the AND gate 23. The output of the inverter 22 is input to the gate of the P-type MOSFET 26.
The flip-flop 21 also has its D input terminal pulled up by the supply voltage Vdd through the terminal 28b. A digital signal F.sub.VCO, the frequency and phase of which is to be compared to the digital reference signal F.sub.REF, is input. The output from the Q terminal of the flip-flop 21 is coupled to the other input terminal of the AND gate 23 through a node B and input to the gate of the N-type MOSFET 27. The output of the AND gate 23 is connected to the reset input terminals of the flip-flops 20 and 21. When the voltage level of the nodes A and B are both high, the output of the AND circuit 23 is high so that the flip-flops 20 and 21 are reset.
The outputs from the Q terminals of the flip-flops 20 and 21 are used to control the MOSFETs 26 and 27. The output of the comparator appears at node O. The output of the supply voltage V.sub.dd appears at node O when MOSFET 26 is on and the output of the ground voltage appears at node O when the MOSFET 27 is on. When both MOSFETs 26 and 27 are off and when there is no input to any of the flip-flops 20 and 21 the output of the comparator is always in a high impedance state.
However, since the output pulse widths at nodes A and B are small when the phase difference between the waveforms F.sub.REF and F.sub.VCO is very small, the output pulse may disappear according to the frequency characteristics of the MOSFETs 26 and 27, resulting in a dead band being formed in the input-output characteristics.